A Novel Technique for Power Optimization in Dual Threshold Footerless Domino Logic Circuit

--In this paper, we proposed a new dual threshold circuit technique for reduction of subthreshold and static power dissipation. When the scaling down technology the threshold voltage takes place, due to increasing the leakage current. In this method, n-type and ptype transistor are introduced between the pull up and pull down network, the gateof inserting transistors is connected to the respective drain regions. For any possible input combination, these transistors introducing stack effect, due to increasing circuit delayin the path supply voltage and ground. Performance can be improved due to reduce the output swing in the circuitry. In this method, the active power consumption is observed at different 25C and 110C temperature variation. The maximum leakage power reduction of 91% is achieved when compared to the base case in a 16nm CMOS technology.